The present invention relates to phase-lock loop circuits. More particularly, the present invention relates to a multiple voltage controlled oscillator phase-locked loop architecture.
Phase-lock loops (PLL) may include a phase-frequency detector (PFD) that provides control signals indicative of a phase difference between a reference clock signal and a feedback clock signal such as a VCO clock of a voltage controlled oscillator (VCO). A charge pump may convert a digital output of the PFD to an analog current (or signal), which may then be integrated by a loop filter to generate a control voltage. The VCO may provide an oscillation signal responsive to the voltage signal.
Advancement in technology scaling is pushing the frequencies over which integrated circuits (such as microprocessors) are operating. At the same time, smaller and smaller feature sizes are causing much higher leakage devices. For this reason, a loop filter capacitance may be implemented using metal wire capacitance. The area of this capacitance may be much larger than previous generations. The area of the loop filter may be about 90 percent of the PLL area. To support a wide frequency range (from very low frequency to very high range) and at the same time achieving optimized performance without further increasing the area or the complexity of the clock generation, multiple PLLs may be utilized each operating at a specific range. However, multiple PLLs using multiple loop filters may require a large area as well as exponentially increase the complexity of the clock generation.